逻辑综合用英语怎么说，逻辑综合的英文翻译

词语导航

基本信息

词语：逻辑综合

繁体：邏輯綜合

拼音：luó jí zōng hé

英语翻译

【计】 logic synthesis

分词翻译

逻辑的英语翻译：

logic
【计】 logic
【经】 logic

综合的英语翻译：

colligate; integrate; synthesize
【计】 uniting
【医】 colligation; synthesis; synthesize
【经】 synthesis

翻译例句

1. 本文阐述的重点是量子电路的可逆逻辑综合问题。

This paper expatiates on synthesis of quantum reversible logic circuits.

2. 本文阐述的重点是量子电路的可逆逻辑综合问题。

The significance, motivation, progress, and challenges was analyzed for reversible logic synthesis of quantum circuit.

3. 设计工作包括系统级设计、RTL级设计、逻辑综合。

The design includes system level design, RTL level design and logic synthesis.

4. 时序逻辑综合是RTL综合系统设计中的一个重要部分。

Sequential logic synthesis is an important part of RTL synthesis system design.

5. 本文给出了适用于大数目输入变量的逻辑综合启发式算法。

We are present a heuristic algorithm of logic synthesis fitted to large number of input variable.

6. 在逻辑综合的领域内，经常使用求给定积项集合补集的过程。

In the area of logic synthesis, a procedure of derivation of complements for a given product set is frequently used.

7. 验证和逻辑综合结果表明DDC芯片能满足设计要求，性能稳定。

Verification and logic synthesis result show that the DDC chip can meet the requirement, also have stable performance.

8. 现在的成功，在商业上的成功逻辑综合可能是由于两个因素造成的。

Now the success of, the commercial success of logic synthesis is probably due to two factors.

9. 上述这些情况可以与您应用程序的逻辑综合使用以便确保缓存内的信息是最新的。

These situations can be used in combination with your application logic to ensure that the information in the cache is up to date.

10. 本文针对pal器件的分析提出一种新型逻辑综合算法，即pls算法。

PLS algorithm is presented as a new logic synthesis algorithm for PAL.

11. 详细介绍了用VHDL语言设计可逻辑综合的教学实验用CPU的过程。

This paper describes a synthetic RISC architecture CPU design and implementation in detail for teaching experiment.

12. 在理论上，逻辑综合工具，保证第一网表是合乎逻辑相当于RTL源代码。

In theory, a logic synthesis tool guarantees that the first netlist is logically equivalent to the RTL source code.

13. 大规模集成PLD器件的逻辑综合是近年来引起广泛关注的热点和难点问题。wwW.wENTiYi.COm

Recent years, being one of the most difficult problems, automatic logic synthesis for large scale PLDs has gained more and more attention.

14. VHDL语言的逻辑综合就是将较高抽象层次的描述自动转换到较低抽象层次描述的一种方法。

The logic synthesis of VHDL language is a method that the description of higher abstract hierarchy is shifted to lower one automatically.

15. 代数拓扑方法用于逻辑综合得到最小覆盖，为了避免可能出现冒险，需要进行冒险问题的讨论。

Method of algebraical topology used in logic synthesis attained least covering, and in order to avoid audaciousness arising, auducious problem was discussed necessarily.

16. 此外，本文提出的方法可以与有限状态机拆分、状态编码和逻辑综合等最先进的优化方法相兼容。

Moreover, the proposed approach is compatible with state-of-the-art methods for finite state machine (FSM) decomposition, state encoding, etc.

17. 提出了一种新的时钟偏斜规划算法，该算法所生成的时序约束可以有效地促进逻辑综合工具的面积优化。

A new clock skew scheduling algorithm is proposed. This algorithm generates timing constraints which can effectively promote the area optimization of logic syn thesis.

18. 逻辑综合的功能是对组合逻辑函数的描述进行转换和优化，生成与逻辑功能描述等价的优化的逻辑级纯结构描述。

Functions of logic synthesis are to transform and optimize the combinational logic functions and produce the pure logic level structural description.

19. 经测试结果表明，基于子集迭代相交算法的逻辑综合系统能够快速、有效的完成大规模数据集合的逻辑综合处理。

The test results show that the developed logic synthesis subsystem can accomplish the cosmic data set processing rapidly and efficiently.

20. 对设计方案的制订、模块化设计流程、模拟仿真、逻辑综合、软硬件协同设计等技术从应用的角度进行了分析研究和掌握。

The technology of constitute scheme, modularize design flow, simulate and emulate, logic synthesis, cooperate with software and hardware has been researched and mastered from the point of application.

21. 由于该时序逻辑综合新方法在处理过程中要涉及解大型覆盖表的问题，为此提出满足压缩状态表约束关系的状态分配的简化算法。

This method, based on combinational logic minimization, proposes a new idea to proceed state assignment according to constrained. relation of compressed state table.

22. 首先介绍了常用并行加法器的设计方法，并在此基础上采用带进位强度的跳跃进位算法，通过逻辑综合和布局布线设计出了一个加法器。

On the basis we design an adder by the adoption of carry skip algorithm with carry strength signals and implement, through logic synthesis and layout.

23. 实验结果表明：按权重分配裕量的方法相对于平均分配裕量，能够在不降低电路性能的情况下，更加有效地降低逻辑综合结果的面积。

Experiment results show that this approach can efficiently reduce area of logic synthesis results compared with the traditional clock skew scheduling algorithm, without degrading the performance.

24. 所有的功能模块组合起来后，通过EDA工具进行CPU内核的逻辑综合和功能仿真，最后在可编程逻辑器件上实现这个完整的CPU内核。

CPU core was simulated and synthesized by EDA tools after combine all units. In the end, CPU core was implemented in programmable logic device.

25. 选拔算法是两级逻辑综合中求解最小化覆盖的经典方法之一，但在输出变量集合和质立方体集合规模较大的情况下，采用选拔法求最小化覆盖存在空间复杂度高、求解时间长等问题。

But as the output variables and the prime implicant grow up, both the long processing time and the resource requirement become the major problems to be resolved with the extraction method.

26. 只有一个综合的，自动的测试组可以发现逻辑错误。

Only a comprehensive, automated test suite can find logic errors.

27. 采用双体船设计的机器人，通过综合传感器反馈回来的信息和模糊逻辑算法进行判断，最后决定在何处开始工作。

Gliding through the water with a catamaran hull the robots will use a combination of feedback from their sensors and fuzzy logic algorithms to determine where to begin working on the oil.

28. 这个级别是通过把2块或更多的硬盘组成一个逻辑卷，逻辑卷的容量大小等于所有磁盘的综合。

This level is achieved by grouping 2 or more hard disks into a single unit with the total size equaling that of all disks used.

29. 这个级别是通过把2块或更多的硬盘组成一个逻辑卷，逻辑卷的容量大小等于所有磁盘的综合。

This level is achieved by grouping 2 or more hard disks into a single unit with the total size equaling that of all disks used.