同学设计的VHDL部分源码如下 为了实现8位数奇偶判断电路 试下述功能描述正确的是： Architecture
同学设计的VHDL部分源码如下，为了实现8位数奇偶判断电路，试下述功能描述正确的是： Architecture a of xor8aa is Signal z1,z2: std_logic; Component xor4c Port（a: IN STD_LOGIC_VECTOR（3 Downto 0); z: out std_logic); end component; Begin
A.U1: xor4c Port map(a3=>a,a2=>b,a1=>c,a0=>d,z=>z1); U2: xor4c Port map(a3=>e,a2=>f,a1=>g,a0=>h,z=>z2); z<=z1 xor z2;
B.U1: xor4c Port map(a(3)<=a,a(2) <=b,a(1) <=c,a(0) <=d,z<=z1); U2: xor4c Port map(a(3) <=e,a(2) <=f,a(1) <=g,a(0) <=h,z<=z2); z<=z1 xor z2;
C.U1: xor4c Port map(a, b, c, d, z1); U2: xor4c Port map(e, f, g, h, z2); z<=z1 xor z2;
D.上述都不准确
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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt4 is port(clk:in std_logic; q:out std_logic_vector(3 downto 0)); end cnt4; architecture one of cnt4 is signal q1:std_logic_vector(3 downto 0); begin process(clk) begin if(clk'event and clk='1')then q1<=q1+1; end if; end process; q<=q1; end one;